環(huán)宇翔
博士，研究員，研究組組長
Email: yxhuan@@www.plm-bat.com
個(gè)人簡介：
環(huán)宇翔，研究員，類腦計(jì)算架構(gòu)與超大規(guī)模處理系統(tǒng)研究組組長，類腦計(jì)算系統(tǒng)研究中心主任。曾于復(fù)旦大學(xué)取得微電子學(xué)與固體電子學(xué)博士學(xué)位，先后任復(fù)旦大學(xué)信息科學(xué)與工程學(xué)院任助理研究員、廣東省智能科學(xué)與技術(shù)研究院副研究員、研究員。環(huán)宇翔博士長期圍繞領(lǐng)域?qū)Ｓ锰幚砑軜?gòu)（Domain-Specific Architecture, DSA）的芯片系統(tǒng)設(shè)計(jì)和領(lǐng)域應(yīng)用開展研究，重點(diǎn)聚焦于從芯片到系統(tǒng)的分布式互聯(lián)處理架構(gòu)和設(shè)計(jì)方法的研究，包括可重構(gòu)可擴(kuò)展架構(gòu)的領(lǐng)域?qū)Ｓ锰幚砥?、深度學(xué)習(xí)模型的高能效加速和分布式處理、神經(jīng)擬態(tài)專用集成電路和超大規(guī)模類腦計(jì)算系統(tǒng)等。環(huán)宇翔博士在智能院工作期間，帶領(lǐng)團(tuán)隊(duì)完成了超大規(guī)模類腦原型驗(yàn)證系統(tǒng)的研制、多尺度可擴(kuò)展的類腦智能計(jì)算芯片研制。其主持和參與了多項(xiàng)國家級(jí)和省部級(jí)項(xiàng)目，已累計(jì)發(fā)表學(xué)術(shù)論文40余篇，申請(qǐng)發(fā)明專利20余項(xiàng)。
類腦計(jì)算架構(gòu)與超大規(guī)模處理系統(tǒng)課題組：
本課題組主要面向類腦計(jì)算的硬件處理架構(gòu)和超大規(guī)模類腦計(jì)算系統(tǒng)設(shè)計(jì)展開研究，旨在借鑒人腦的信息處理機(jī)制，設(shè)計(jì)具有神經(jīng)擬態(tài)特性的專用處理內(nèi)核、大規(guī)模的芯片互聯(lián)架構(gòu)與方法、以及面向全腦尺度千億神經(jīng)元規(guī)模超級(jí)計(jì)算系統(tǒng)。課題組將主要聚焦：面向類腦計(jì)算的領(lǐng)域?qū)Ｓ锰幚砑軜?gòu)與芯片設(shè)計(jì)，超低延時(shí)和高可靠的片上網(wǎng)絡(luò)互聯(lián)，面向晶圓級(jí)集成芯片的新型片上分布式處理架構(gòu)和任務(wù)調(diào)度方法。目標(biāo)通過“算法-架構(gòu)-電路”協(xié)同設(shè)計(jì)的方法，實(shí)現(xiàn)事件驅(qū)動(dòng)的超大規(guī)模芯片計(jì)算網(wǎng)絡(luò)，支持海量處理內(nèi)核的局部數(shù)據(jù)共享、異步信息傳遞和分布式協(xié)同處理，最終支撐千億神經(jīng)元規(guī)模的類腦計(jì)算系統(tǒng)的設(shè)計(jì)構(gòu)建。
本課題組面向（智能計(jì)算芯片架構(gòu)設(shè)計(jì)、智能算法編譯優(yōu)化方向、并行計(jì)算軟硬件協(xié)同優(yōu)化等方向）招聘博士后、工程師、實(shí)習(xí)生，感興趣的同學(xué)，請(qǐng)郵件聯(lián)系。
代表論著：
[1] J. Xu, J.Fan, B. Nan, C. Ding, L. Zheng, Z. Zou, Y. Huan*, "ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2023. (SCI，通信作者)
[2] H. Jia#, Y. Huan#*; C. Ding, Y. Yan, J. Cui, J. Wang, C. Cai, L. Xu, Z. Zou*, L. Zheng*, "ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization," in IEEE Transactions on Industrial Informatics, 2022. (SCI，共同一作，共同通信作者)
[3] C. Ding#, Y. Huan#*, H. Jia, Y. Yan, F. Yang, L. Liu, M. Shen, Z. Zou and L.R. Zheng, "A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022. (SCI，共同一作，共同通信作者)
[4] B. Huang#, Y. Huan#*, H. Jia, C. Ding, Y. Yan, B. Huang, L.R. Zheng, and Z. Zou, "AIOC: An All-In-One-Card Hardware Design for Financial Market Trading System," in IEEE Transactions on Circuits and Systems II: Express Briefs, 2022. (SCI，共同一作，共同通信作者)
[5] Y. Jin, B. Huang, Y. Yan; Y. Huan*, J. Xu, S. Li, P. Gope, L. Xu, Z. Zou, and L.R. Zheng, "Edge-based Collaborative Training System for Artificial Intelligence-of-Things," in IEEE Transactions on Industrial Informatics, 2022. (SCI，共同通信作者）
[6] B. Huang#, Y. Huan#*, H. Chu, J. Xu, L.R. Zheng, and Z. Zou, “IECA: An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm2 Area Efficiency,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2021. (SCI，共同一作，通信作者)
[7] J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture,” in IEEE Transactions on Circuits and Systems II: Express Briefs, 2020. (SCI，共同一作)
[8] Y. Huan, N. Ma, J. Mao, S. Blixt, Z. Lu, Z. Zou and L. R. Zheng, “A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2016. (SCI)
[9] Y. Jin, J. Cai, J. Xu, Y. Huan*, Y. Yan, B. Huang, Y. Guo, L.R. Zheng, Z. Zou, “Self-aware distributed deep learning framework for heterogeneous IoT edge devices,” Future Generation Computer Systems, 2021. (SCI，通信作者)
[10] W. Li, H. Chu, B. Huang, Y. Huan*, L.R. Zheng, Z. Zou, “Enabling on-device classification of ECG with compressed learning for health IoT,” Microelectronics Journal, 2021. (SCI，通信作者)
[11] J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks,” in Journal of Signal Processing Systems, 2020. (SCI，共同一作)
[12] Y. Huan, J. Xu, L. Zheng, H. Tenhunen and Z. Zou, “A 3D Tiled Low Power Accelerator for Convolutional Neural Network,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018. (EI)
