賈浩
博士后
Email：jiahao@@www.plm-bat.com
研究方向：
類腦芯片與系統(tǒng)集成
個(gè)人簡(jiǎn)介：
2018年本科畢業(yè)于電子科技大學(xué)電子科學(xué)與工程學(xué)院集成電路設(shè)計(jì)及集成系統(tǒng)專業(yè)，2023年于復(fù)旦大學(xué)取得電子信息博士專業(yè)學(xué)位。博士期間圍繞領(lǐng)域?qū)Ｓ锰幚砑軜?gòu)（Domain-Specific Architecture, DSA）的芯片系統(tǒng)設(shè)計(jì)和領(lǐng)域應(yīng)用開展研究。參與國(guó)家自然科學(xué)基金、上海市新一代人工智能市級(jí)重大專項(xiàng)等多項(xiàng)課題，具體研究?jī)?nèi)容包括類腦計(jì)算芯片與系統(tǒng)、超低延時(shí)行情數(shù)據(jù)分發(fā)系統(tǒng)等。完成了粗細(xì)粒度可重構(gòu)的類腦計(jì)算系統(tǒng)FPGA原型樣機(jī)和ASIC芯片，以及超低延時(shí)行情數(shù)據(jù)分發(fā)系統(tǒng)FPGA樣機(jī)等工作，相關(guān)研究成果共發(fā)表6篇學(xué)術(shù)論文，并申請(qǐng)發(fā)明專利2項(xiàng)。
代表論著：
1. H. Jia, Y. Huan, C. Ding, Y. Yan, et al., "A Domain-Specific Accelerator for Ultra-low Latency Market Data Distribution System," in IEEE Transactions on Industrial Informatics, vol. 19, no. 4, pp. 5465-5475, April 2023.
2. C. Ding, Y. Huan, H. Jia, Y. Yan, et al., "A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 5, pp. 1990-2001, May 2022.
3. B. Huang, Y. Yan, H. Jia, C. Ding, et al., "AIOC: An All-in-One-Card Hardware Design for Financial Market Trading System," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 9, pp. 3894-3898, Sept. 2022.
4. H. Chu, Y. Yan, L. Gan, Hao Jia, et al., "A Neuromorphic Processing System With Spike-Driven SNN Processor for Wearable ECG Classification," in IEEE Transactions on Biomedical Circuits and Systems, vol. 16, no. 4, pp. 511-523, Aug. 2022.
5. H. Chu, H. Jia, Y. Yan, Y. Jin, et al., "A Neuromorphic Processing System for Low-Power Wearable ECG Classification," 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), Berlin, Germany, 2021, pp. 1-5.
6. C. Ding, Y. Huan, H. Jia, Y. Yan, et al., "An Ultra-Low Latency Multicast Router for Large-Scale Multi-Chip Neuromorphic Processing," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4.
